Today the world of communication has minimized as the trends in digital communication is reaching its high. The digital signal processing has become the heart and soul of digital communication, digital applications such as image processing, voice processing, and digital filtering applications. The MAC unit which is drawn most importance in the DSP, has to concerned at much greater part. Optimizing the MAC unit plays a major role in DSP applications, optimizing the MAC require to cut down the two parameters: Power and Latency. The design of the MAC unit is based on the Vedic multiplier and the Reversible DKG gate. The Vedic multiplier is designed with the ancient Indian mathematics based on Atharvana Veda called “Urdhva Triyakbhyam. The adder unit is design with the Reversible Logic DKG adder. The reversible logic is one of the emerging out technology which is the future of Quantum computing. It has the advantage of least power consumption. The increasing trends in the VLSI and Low power design have increased the need of low power dissipation circuits to be designed. The Vedic Multiplier has the advantage of generating the partial products with reduce number and decreasing the latency. The MAC unit design is programmed using Verilog - HDL using Xilinx ISE 14.7. The FPGA implementation is done on Spartan3E.
Keywords: Vedic multiplier, Reversible DKG gate component, Urdhva Triyakbhayam
1. Dhaval Bhathia “ Vedic Mathematics made easy”, Bhatiya, 1988.
2. Jagadguru Swami Sri Bharati Krishna Tirthji Maharaja,“Vedic Mathematics”, Motilal Banarsidas, Varanasi, India, 1986.
3. Harpreet Singh Dhillon and Abhijit Mitra, “A Reduced- Bit Multiplication Algorithm for Digital Arithmetics”, International Journal of
Computational and Mathematical Sciences 2;2 © www.waset.org Spring 2008.
4. Shripad Kulkarni, “Discrete Fourier Transform (DFT) by using Vedic Mathematics”, report, vedicmathsindia.blogspot.com, 2007.
5. Himanshu Thapliyal, Saurabh Kotiyal and M. B Srinivas, “Design and Analysis of A Novel Parallel Square and Cube Architecture Based On Ancient Indian Vedic Mathematics”, Centre for VLSI and Embedded System Technologies, International Institute of Information Technology, Hyderabad, 500019, India, 2005, IEEE.
6. Shamim Akhter, “VHDL Implementation of Fast NXN Multiplier Based on Vedic Mathematics”, Jaypee Institute of Information Technology University, Noida, 201307 UP, INDIA, 2007, IEEE.
7. R. Landauer, “Irreversibility and Heat Generation in the Computing Process,” IBM journal of Research and Development, vol. 5, no. 3, pp. 183–191, Jul. 1961.
8. C. H. Bennett, “Logical Reversibility of Computation,” IBM Journal of Research and Development, vol. 17, no. 6, pp. 525–532, 1973.
9. Abhijeet Kumar, Dilip Kumar, Siddhi, “Hardware Implementation of 16*16 bit Multiplier and Square using Vedic Mathematics”, Design Engineer, CDAC, Mohali.