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JOURNALS || ASIO Journal of Engineering & Technological Perspective Research (ASIO-JETPR) [ISSN: 2455-3794]
Optimized 64 Bit Mac Using Vedic Multiplier And Reversible Logic For Dsp Application

Author Names : C. Devika
Page No. : 10-15  volume 2 Issue 3
Article Overview

Today the world of communication has minimized as the trends in digital communication is reaching its high. The digital signal processing has become the heart and soul of digital communication, digital applications such as image processing, voice processing, and digital filtering applications. The MAC unit which is drawn most importance in the DSP, has to concerned at much greater part. Optimizing the MAC unit plays a major role in DSP applications, optimizing the MAC require to cut down the two parameters: Power and Latency. The design of the MAC unit is based on the Vedic multiplier and the Reversible DKG gate. The Vedic multiplier is designed with the ancient Indian mathematics based on Atharvana Veda called “Urdhva Triyakbhyam. The adder unit is design with the Reversible Logic DKG adder. The reversible logic is one of the emerging out technology which is the future of Quantum computing. It has the advantage of least power consumption. The increasing trends in the VLSI and Low power design have increased the need of low power dissipation circuits to be designed. The Vedic Multiplier has the advantage of generating the partial products with reduce number and decreasing the latency. The MAC unit design is programmed using Verilog - HDL using Xilinx ISE 14.7. The FPGA implementation is done on Spartan3E.

Keywords: Vedic multiplier, Reversible DKG gate component, Urdhva Triyakbhayam

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